Senior ASIC Timing Engineer — Equity + High-Impact Innovation

Google Sunnyvale, CA, USA is seeking a Static Timing Engineer to lead the timing closure for high-performance compute ASICs. You will develop constraints, automate timing flows, and collaborate with architecture, logic design, and DFT teams to meet tight performance and power goals. You will work on advanced technology nodes, develop methodologies, and evaluate vendors/tools. In-person interviews are typically required as part of the hiring process.