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Lead ASIC DFT & DV Engineer

L6

ciscoSan Jose, CAyesterday
Cisco Systems, Inc. in San Jose, CA is seeking a DFT Verification Lead within the Silicon One team. This hybrid role requires three days per week on-site at Cisco's San Jose location and involves test planning, test bench development, and DFT architecture to support ATE screening and in-system test. You will collaborate with Front-end RTL and backend PD teams, driving high-quality DFT verification and debugging with minimal mentorship. Strong SystemVerilog and scripting skills are essential.
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Level

LeadL6

Location

San Jose, CA

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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