VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS (10+ Yrs)

L6

dexianFolsom, CAyesterday
VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS Folsom, CA3 + Months Role: Lead block-level physical design from RTL to GDSII.
Must Have: 10+ years exp, advanced nodes, and Fusion Compiler. Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.
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Level

LeadL6

Location

Folsom, CA

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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