Senior Clocks ASIC Design Engineer - RTL & PPA Innovation

NVIDIA in Austin, TX is seeking an ASIC clock engineer to own the clock domain across GPU/CPU design. You will optimize PPA, evaluate clocking topologies in RTL, and work with floorplanning and timing teams to enable high-speed clocks. This role emphasizes collaboration, RTL design, and silicon bringup across cross-disciplinary teams. Must have a BS in Electrical Engineering (MS preferred) and 3+ years' experience in RTL/Verilog, Python, and clocking in advanced chips.