Lead DFT & Production Silicon Architect

Fortell is seeking an experienced DFT Engineer to lead full-chip test architecture, collaborating across STA, physical design, memory, and test teams to deliver production-ready silicon with robust test coverage. You will develop DFT structures (full-scan, boundary scan, memory test), implement test infrastructure using Cadence Genus/Modus, and generate ATPG vectors. The role requires Bay Area residency and occasional in-person collaboration.