Senior Hardware Development Engineer, Cloud AI/ML Server Team

What You Will Do: Define the hardware that runs the world's largest AI training workloads. Your designs span electrical, thermal, mechanical, power, and signal integrity across GPU-accelerated platforms. Drive validation from first silicon through fleet-scale deployment, triage failures correlating across PCIe, power delivery, memory, and accelerator interconnects, and feed root cause findings back into design improvements. When a new server platform launches at a large scale, the architecture, component choices, and quality gates are yours. Why You Will Love ItThe world's most advanced frontier models train on the hardware you design. You will see your architecture decisions scale to a large fleet of servers. The team is deeply technical and high-trust — you own platforms end to end from architecture definition through fleet operations.

The Ideal Candidate: You think across the full hardware stack — from silicon packaging and power delivery to rack-level thermal and mechanical design. You are as comfortable reviewing a schematic as you are analyzing fleet failure data. You drive quality through data, not assumption, and you hold design partners to the same standard you hold yourself. You mentor and develop junior engineers, contribute to hiring, and share your expertise to make the team stronger. Key job responsibilities Architecture & DesignDefine server architectures based on workload demand and customer requirements, translating them into detailed designs and component specifications that enable high-performance AI training and inference at scale Work with interdisciplinary teams of component, firmware, test, qualification, and integration engineers to deliver cohesive designs Drive design reviews with ODM/JDM partners covering schematic, layout, BOM, and manufacturing DFx (Design for Test, Design for Manufacturing) Validation & Bring-upDefine and execute validation strategies from PCBA bring-up through server and rack integration — covering power sequencing, signal integrity, thermal characterization, and accelerator interconnect performance Own hardware debug during EVT/DVT/PVT builds, correlating failures across PCIe, power rails, memory channels, and GPU subsystems Triage hardware issues at both ODM facilities and datacenters, conduct root cause analysis, and implement corrective actions Fleet Quality & Continuous Improvement Own fleet quality metrics post-launch: server-level annualized failure rates and component-level failure modes Monitor operational telemetry to identify systemic issues and drive design or process changes for current and future platforms Partner with test and automation teams to improve manufacturing yield and reduce test dwell times Cross-Team Collaboration Work with EC2 architecture teams to align on instance definitions, workload requirements, and platform trade-offs Drive ODM/JDM design partners through development milestones and production ramp Collaborate with firmware, software, and operations teams to ensure designs are debuggable, serviceable, and automation-ready May require occasional (