Physical Design Engineer, Annapurna Labs

Responsibilities: Collaborate with RTL/logic designers to conduct architectural feasibility studies and assess power-performance-area tradeoffs for physical design closure. Lead the physical implementation of IO/Core blocks through synthesis, floor planning, bus/pin planning, place and route, and power/clock distribution. Perform congestion analysis, timing closure, IR drop analysis, physical verification, ECO, and sign-off processes. Develop and refine physical design methodologies. Evaluate third-party IP and provide informed recommendations. Foster a collaborative environment with other physical design engineers and RTL/Architecture teams.

Qualifications: Bachelor's degree in Electrical Engineering or a related field. Proven experience in identifying bugs in architecture, algorithms, functionality, and performance with strong debugging skills. Experience in verifying at multiple levels of logic.

Skills: Strong collaboration and teamwork abilities. Expertise in physical design tools and methodologies. Knowledge of ASIC design processes and best practices. Find the Right Semiconductor PartnerASIC Design Services Verification Packaging & Wafer Semiconductor IP Work Email Free No obligation Response within 24 hours