Lead ASIC Architect – High-Performance AI Chips (Hybrid)

Cisco Systems, Inc. is seeking a senior ASIC verification engineer to drive the definition, architecture and verification of high-performance ASICs in a San Jose environment. The role involves owning multiple functional areas, developing reusable code, and debugging across ASIC, software, and hardware levels. The candidate will lead DV work, define new verification methodologies, and collaborate with ASIC and apps teams to resolve architectural issues, while contributing to lab bring-up and