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Hybrid OPC R&D Engineer: Patterning & Tapeout Lead

L6

solidigmSan Jose, CAyesterday
Solidigm is seeking a Lead OPC R&D Engineer to develop and guide high-quality patterning solutions for memory devices. You will model and correct optical effects, drive SMO and DFM techniques, and ensure the final layout transfers accurately to wafers while meeting manufacturing requirements. In this hybrid US-based role, you will collaborate with design, TD, lithography, and manufacturing teams, mentor colleagues, and contribute to documenting processes and training internal teams.
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Apply now (opens in a new tab)

Level

LeadL6

Location

San Jose, CA

Occupation

Microsystems Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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