Senior Digital ASIC Engineer — High-Performance, Low-Power

Draper Laboratory seeks a Senior Digital ASIC Designer to deliver high-performance digital ASICs in advanced technologies. You will implement designs from RTL through synthesis, work with multi-disciplinary teams, and contribute to multiple projects across applications. The role requires strong front-end digital design skills, experience with Cadence or Synopsys, and the ability to lead teams. An active US secret clearance is required for onsite work in Cambridge, MA.