Senior Design Verification Engineer: PCIe/UALink for AI Infra

Astera Labs in San Jose, CA, seeks a Senior Design Verification Engineer to define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner with RTL, architecture, firmware and post-silicon teams to build verification strategies proving complex switching across high-bandwidth protocols and demanding system environments. This role spans planning, testbench architecture, coverage closure and silicon learning, contributing