Senior IC Physical Design Engineer - Synthesis to Signoff

Arrow Electronics is seeking a Physical Design Engineer II to drive ASIC partition implementation, including synthesis, place-and-route, and timing convergence. You will collaborate with architects, RTL designers, and DFT engineers to resolve issues and ensure clean signoffs. Strong PD flow expertise and TCL scripting are highly valued. The role requires 7+ years in physical design, proficiency with Innovus/Tempus/Quantus, and experience in SoC design and sub-7nm processes.