Sr. High Speed Digital Design Engineer

Duration: 6-Month Contract (Possible Extension)

Location: Gilbert, AZ 85233 (Onsite)

Schedule: 9/80, Mon-Thurs: 7:30am-5:00pm & Fri: 7:30am-4:00pm Key Responsibilities• Architect FPGA-, ASIC-, and processor-based digital hardware for high-reliability systems.• Lead digital hardware design including architecture, schematics, interface definition, timing constraints, and design reviews.• Design, integrate, and verify high-speed digital interfaces such as DDR, PCIe, Ethernet, Ser Des, LVDS, SPI, I2C, or similar technologies.• Support board bring-up, hardware integration, debug, and system verification using standard laboratory equipment.• Partner with PCB layout engineers to optimize signal integrity, power integrity, timing, and manufacturability.• Develop and review technical documentation including architecture documents, interface specifications, design reviews, test plans, and verification reports.• Provide technical mentorship and engineering leadership across multidisciplinary teams.• Ensure designs satisfy aerospace and defense performance, reliability, environmental, and quality requirements.

Required Qualifications: • Bachelor's degree in electrical engineering, Computer Engineering, or related field.• 8+ years designing complex digital hardware for aerospace, defense, communications, embedded computing, or other high-reliability products.• Experience designing FPGA-, ASIC-, processor-, or SoC-based digital systems.• Experience with board bring-up, hardware integration, and laboratory debug.• Experience with high-speed digital interfaces and timing analysis.• Experience with signal integrity principles and collaboration with PCB layout teams.• Excellent communication, technical leadership, and cross-functional collaboration skills.

Preferred Qualifications: • Master's degree in electrical or computer engineering.• Experience developing aerospace or defense electronics.• Experience with radiation-tolerant or harsh-environment electronics.• Experience with formal verification, power integrity, and mixed-signal hardware.