Senior SoC Physical Design Engineer (7nm/5nm)

SK hynix memory solutions America Inc. is seeking a Sr. Staff Physical Design Engineer to lead high-performance SoC integration, driving physical implementation from RTL to GDS while collaborating with front-end, DFT, power, and analog teams to optimize PPA and ensure timely tapeouts. The role demands hands-on expertise in 7nm/5nm/3nm processes, strong scripting in Tcl/Python, and leadership to mentor junior engineers in a collaborative environment.