VP, Physical Design & Chiplet Architecture

Astera Labs seeks a VP of Physical Design to lead full-chip physical design for next-generation switching products with UCIe and UALink. You will drive multi-die architectures, tapeouts, and performance targets in collaboration with architecture, digital design, packaging, and silicon teams. You will mentor a growing PD team, ensure robust timing closure, power and area optimization, and lead efforts across 7nm or below node implementations.