Senior ASIC Physical Design Engineer

Key Responsibilities: Support floorplanning, macro placement, and power planning for AI accelerator designs Drive clock tree synthesis, place and route, and timing closure on assigned blocks Execute Innovus-based implementation flows and partner with backend design services for strategy alignmentRequired Qualifications 5-8 years of experience in physical design, from floorplanning to tapeout Proficiency in Innovus and/or ICC2 implementation flows Strong knowledge of physical implementation processes, including timing and power closure Experience with advanced-node tapeouts and signoff across quality metrics Hands-on expertise in tools such as Tempus, PrimeTime, Voltus, RedHawk, and Calibre