Senior Design Verification Engineer - Memory Controller Subsystem (HBM)
altenSan Jose, CA
Senior Design Verification Engineer - Memory Controller Subsystem (HBM)
L6
altenSan Jose, CAyesterday
Industries
Computer Systems Design ServicesElectronic Computer ManufacturingSemiconductor and Related Device ManufacturingExperience: 5–12+ Years
Responsibilities: Verify the HBM-based Memory Controller subsystem using SystemVerilog/UVM.
Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
Verify the HBM protocol, memory transactions, scheduling, ECC, QoS, power management, and performance.
Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
Collaborate with Architecture, RTL, and Validation teams through verification signoff.
Required Skills: Strong SystemVerilog/UVM expertise.
Experience verifying DDR/HBM memory controllers or memory subsystems.
Good understanding of HBM/DDR protocols, AXI interfaces, and memory architecture.
Experience with assertions, constrained‑random verification, coverage closure, and VIP integration.
Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).
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Level
LeadL6
Location
San Jose, CA
Occupation
Validation Engineers
Industry
Computer Systems Design Services
Posted
yesterday
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