Key Responsibilities:
Deeply understand what is involved in physical designRunning PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD infrastructureCollaborate with RTL Designers and provide Physical Design feedback to improve PPADrive dashboards that show the convergence of projects related to PDOptimize tool flows, working with EDA vendors to incorporate the latest featuresAccountable for block level closureSupervise the outsourcing of physical design to a 3rd party serviceYou may be a good fit if you have 5-10+ years of previous experience with PDTools, flow, and design methodology from RTL synthesis to GDSII sign-offExperience with back-end design and timing closure on advanced process nodes (5nmand below) Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler)automated RTL-to-GDSII flowsExperience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysisDeeply creative and able to think from first principlesStrong candidates may also have experience withFamiliarity with modern ML and LLM model architecturesAbility to program with Python or another scripting languageFamiliarity with AI tools for programming/codingStartup experience or comfort working in fast-paced environments