Senior Engineer - Physical Design

Location: Austin, TX (or) San Diego, CA (or) Santa Clara, CA

Duration: 6 months

Job Description: We are seeking highly motivated Physical Design Engineers across multiple career levels to join our growing ASIC implementation team. In this role, you will contribute to the development and execution of advanced physical design methodologies for complex, high-performance, low-power SoCs and IP blocks. You will work closely with architecture, RTL, DFT, verification, CAD, and product engineering teams to implement and deliver industry-leading designs from synthesis through final tapeout. The ideal candidate possesses strong technical expertise in physical implementation, timing closure, low-power design techniques, automation, and design optimization. Depending on experience and demonstrated technical leadership, candidates may be considered for Engineer, Senior Engineer, Staff Engineer, or Principal Engineer opportunities. Physical Design responsibilities include floorplanning, power planning, place and route, clock tree synthesis, timing closure, signal integrity analysis, physical verification, ECO implementation, and design signoff activities.

Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. ORMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. ORPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Experience with digital ASIC physical implementation methodologies. Understanding of power, performance, area, timing, and physical design tradeoffs. Experience working in Linux/Unix environments. Programming or scripting experience utilizing Python, Tcl, Perl, Shell, or similar languages. Strong analytical, problem-solving, and debugging skills.

Preferred Qualifications: Experience with complete Physical Design Flow from synthesis through tapeout. Physical design expertise including floorplanning, power planning, placement, CTS, routing, timing optimization, and closure. Experience using Cadence Innovus and/or Synopsys Fusion Compiler. Static Timing Analysis and timing closure experience using Synopsys PrimeTime. Knowledge of MMMC implementation methodologies and advanced-node design closure. Experience with DFT-aware implementation and functional timing constraints. Experience with RC extraction, signal integrity analysis, cross-talk analysis, ECO implementation, and formal verification. Experience with low-power implementation techniques, UPF methodologies, and power domain analysis. Strong communication, collaboration, and technical leadership capabilities.