Synthesis-DFT Stitch CAD Engineer

Company: Qualcomm Technologies, Inc. Job Area:

Engineering Group, Engineering Group > ASICS Engineering General Summary: Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of gate-level synthesis and DFT stitch solutions for the Snapdragon chips powering billions of mobile devices. The position requires Synthesis, DFT, Place and Route exposure and CAD development skills to define and develop implementation tools and methodologies for PPA, shortening design cycle time, in close collaboration with Snapdragon Design and Implementation teams. Qualcomm is using leading edge internal and EDA technologies in the Implementation domain, including pioneering in genAI/ML, and developing good-by-construction automation and PPA recipes for the most complex designs of the industry in terms of multi-voltage and Fmax-area-power goals. This role's responsibilities will include: Participating in the development of Qualcomm DFT stitch flow and methods, leveraging both Synopsys and Cadence solutions and tools. Improving the SoC Synthesis and DFT Stitch methodologies for diverse Mobile, Compute, AI, IoT Snapdragon chips. Enabling new features from EDA tools or/and internal tools for Synthesis, DFT Stitch checks. Development and support of methodology to handle complex multi-voltage crossings on DFT paths Support Snapdragon design teams on CAD solutions, analyze their requests, and address their requests through ticket queues. Interfacing with EDA vendors to enable production-ready tool sets that satisfy project's requirement. Setting up, augmenting, and maintaining a regression of complex DFT Stitch and Synthesis testcases. Innovating with design/tool/flow techniques for area reduction, dynamic power reduction and turn-around time, leading to participation to patents.